Electronic ballasts for fluorescent lamps typically can be analyzed as comprising a “front-end” and a “back-end”. The front-end typically includes a rectifier for changing alternating-current (AC) mains line voltage to a direct-current (DC) bus voltage, and a filter circuit, e.g., a capacitor, for filtering the DC bus voltage. The front-end of electronic ballasts also often includes a boost converter, which is an active circuit for boosting the magnitude of the DC bus voltage above the peak of the line voltage and for improving the total harmonic distortion (THD) and the power factor of the input current to the ballast. The ballast back-end typically includes a switching inverter for converting the DC bus voltage to a high-frequency AC voltage, and a resonant tank circuit having a relatively high output impedance for coupling the high-frequency AC voltage to the lamp electrodes.
Referring first to FIG. 1, there is shown a simplified block diagram of a prior art electronic ballast 100. The ballast 100 includes a front-end 102 for producing a substantially DC bus voltage across a bus capacitor, CBUS, from an AC input voltage. The ballast 100 further comprises an inverter 104 for converting the DC bus voltage into a high-frequency voltage for driving a lamp current in a fluorescent lamp 108. The high-frequency voltage provided by the inverter 104 is coupled to the lamp 108 through a resonant tank 106 having a resonant inductor, LRES, and a resonant capacitor, CRES.
The inverter 104 includes first and second series-connected switching devices 112, 114 and a gate drive circuit 116. The switching devices 112, 114 in the inverter 104 are controlled using a d(1−d) complementary switching scheme. In the d(1−d) complementary switching scheme, the first switching device 112 has a duty cycle of d and the second switching device 114 has a duty cycle of 1−d. The switching devices 112, 114 are controlled by the gate drive circuit 116 such that only one switching device is conducting at a time. When the first switching device 112 is conducting, then the output of the inverter 104 is pulled upwardly toward the DC bus voltage. When the second switching device 114 is conducting, then the output of the inverter 104 is pulled downwardly toward circuit common.
The current through the lamp 108 is controlled by changing the frequency and/or the duty cycle of the high-frequency voltage at the output of the inverter 104. A current sense circuit 110 is coupled in series with the lamp 108 and provides a lamp current signal 250 representative of the magnitude of the current through the lamp. An analog control circuit 210 is responsible for controlling the gate drive circuit 116 and thus the switching devices 112, 114 of the inverter 104. The analog control circuit 210 includes a reference circuit 212, a summing circuit 214, a compensator circuit 216, a frequency-shift circuit 218, a triangle-wave oscillator 222, and a comparator 220. The reference circuit 212 provides a reference signal 242 representative of a target current ITARGET for the lamp 108. The summing circuit 214 receives the lamp current signal 250 and the reference signal 242 and creates an error signal 240 representative of the difference between the target current and the actual current in the lamp 108. The compensator circuit 216 receives the error signal 240 and provides a duty cycle request voltage 246 that is proportional to the desired duty cycle of the inverter 104.
The frequency shift circuit 218 also receives the reference signal 242 and provides a desired frequency signal 245 representative of the desired inverter frequency. The triangle-wave oscillator 222 receives the desired frequency signal 245 from the frequency shift circuit 218 and provides a triangle-wave signal 244 at the desired frequency. The comparator 220 receives both the triangle wave signal 244 and the duty cycle request voltage 246 and produces a pulse width modulated (PWM) signal 248 with the desired frequency and duty cycle. This PWM signal 248 is provided to the gate drive circuit 116, which drives the switches 112, 114 in the inverter 104.
In addition to the normal running mode, the ballast 100 has several other modes of operation including a “preheat” mode and a “strike” mode. The purpose of the preheat mode is to heat the lamp filaments prior to the application of a sufficient voltage to strike the lamp. During the strike mode, the lamp voltage is increased until either the lamp strikes or a predetermined voltage limit is reached.
Preheat is accomplished by controlling the frequency of the inverter 104 to a preheat frequency, which is greater than the frequency of the inverter 104 in normal operation. During preheat, the compensator circuit 216 is always in control of the duty cycle of the inverter 104. At the same time, the reference circuit 212 provides a reference signal 242 at a level that represents a non-zero lamp current. Since there is no current through the lamp during preheat, the current sense circuit 110 produces the lamp current signal 250 with a positive magnitude and thus the output of the summing circuit 214, i.e., the error signal 240, has a non-zero value. The compensator circuit 216 includes an integrator (not shown), so the non-zero error signal 240 causes the compensator circuit 216 to increase the duty cycle of the duty cycle request voltage 246 to 50%, at which time the compensator circuit saturates. At this point, the duty cycle of the duty cycle request voltage 246 is fixed at 50% and the preheat voltage is adjusted by changing the frequency. It is important to note that since the compensator circuit 216 contains an integrator, it is not possible to set the duty cycle to an arbitrary level. In practice, the choices would be saturated at 50% or saturated at 0%. An alternative would be to provide additional circuitry to clamp the output of the compensator circuit 216 at a given level during preheat, but this would add additional cost and complexity.
To strike the lamp 108, i.e., in the strike mode, the operating frequency of the inverter 104 is swept down from the preheat frequency to a low-end frequency. Preferably, the low-end frequency is near the resonant frequency ωR of the resonant tank 106, i.e., ωR=1/√{square root over ((LRES*CRES))}. Accordingly, the voltage at the output of the resonant tank 106 at the low-end frequency is substantially large and is appropriate to strike the lamp 108. When the lamp 108 strikes, the lamp current begins to flow through the lamp. At this time, the compensator circuit 216 of the analog control circuit 210 is still saturated and the duty cycle of the duty cycle request voltage 246 is still 50%. As a result, a current above the target current starts to flow through the lamp 108. This excess current will cause the compensator circuit 216 to come out of saturation and to set the duty cycle of the PWM signal 248 so as to maintain the target current in the lamp 108. While the compensator circuit 216 is saturated, the current in the lamp 108 can be significantly higher than the target current. The high current, along with the time required for the loop to come out of saturation, can result in a noticeable flash when the lamps strike.
A simplified schematic diagram of another prior art electronic ballast 300 is shown in FIG. 2. The ballast 200 operates in a similar manner as the ballast 100 shown in FIG. 1, but the analog control circuit 210 has been replaced by a digital control circuit 310. An analog-to-digital converter (ADC) 352 in a microprocessor 350 receives the lamp current signal 250 from the current sense circuit 110 and converts it into an 8-bit digital representation. The reference signal 242 representative of the target current in the lamp 108 is received at an input 355. The software in the microprocessor 350 then compares the measured current with the target current to generate an error signal, which is then used to generate a desired duty cycle. The desired frequency is determined from the desired current. A pulse-width modulated (PWM) signal 356 is produced at an output 354 of the microprocessor 350. The software in the microprocessor 350 drives the PWM signal 356 with the desired frequency and duty cycle and provides the PWM signal to the gate drive circuit 116. In the ballast 300, software in the microprocessor 350 of the digital control circuit 310 provides the functionality that was provided by the analog control circuit 210 of the ballast 100.
The digital implementation of the preheat mode of the ballast 300 is very different than the preheat mode of the ballast 100. The software that normally implements the compensator routine is not in control of the inverter duty cycle. In fact, a completely different routine is in control of the inverter. As a result, it is possible to directly control both the duty cycle and the frequency to achieve the desired preheat level.
In the digital implementation of the strike mode, the duty cycle is held at a fixed level and the frequency is swept down from the preheat frequency to the low-end frequency. During this period, the software must monitor the lamp voltage and lamp current to detect when the lamp strikes. It is very important to detect when the lamp strikes because once it is struck, a different routine must be run to implement the normal operation control loop. Since both the frequency and duty cycle are controllable during strike, it would be possible to set the duty cycle to something less than 50% during the strike phase. The lower duty cycle would result in the lamp starting at a lower current to help reduce flash. However, in order to ensure accurate detection of lamp strike, the lamp must strike with a relatively high current.
Replacing the analog control circuit 210 of the ballast 100 with the digital control circuit 310 of the ballast 300 has several benefits. First, there are fewer parts in the digital control circuit 310 since most of the control functions are completed by the microprocessor 350. Second, the control functions provided by the microprocessor 350 can be easily altered without the need to change any hardware of the digital control circuit 310. Further, situation-specific software can be executed when the ballast 300 is in different normal and abnormal modes of operation.
However, the digital control circuit 310 has some disadvantages in view of the analog control circuit 210. The capability of the microprocessor 350 is dependent on the cost of the device. So, in order to achieve a reasonable cost, some compromises may need to be made in the areas of core speed, ADC resolution, ADC sampling rate and math capability. Quantization effects of the ADC conversion can become significant at low dim levels. This can be improved with a higher resolution ADC or a higher sampling rate, but as mentioned earlier, higher capability results in higher cost for the microprocessor 350.
Both the analog control circuit 210 and the digital control circuit 310 of the prior art ballast 100, 300 use an open-loop frequency shift in which there is a predetermined operating frequency for a given desired light level. The concept of adjusting both the frequency and the duty cycle of the inverter 104 is described in greater detail in U.S. Pat. No. 6,452,344, issued Sep. 17, 2002, entitled “Electronic Dimming Ballast”, which is hereby incorporated herein by reference in its entirety.
FIG. 3 is a simple control system diagram illustrating the control loops of the prior art ballasts 100, 300. The operating duty cycle, dOP, of the inverter is controlled through a closed-loop technique, while the operating frequency, fOP, is controlled through an open-loop technique. The actual lamp current, IACTUAL, is provided as feedback to the duty-cycle control loop and is subtracted from the target current, ITARGET, to produce a lamp current error signal, eI, and ultimately, the desired operating duty cycle dOP. In contrast, the desired operating frequency fOP is simply generated solely in response to the target current ITARGET.
FIG. 4 shows a plot of the target operating frequency of the inverter 104 versus the lamp current and a plot of the operating frequency versus the lamp current at a fixed 50% duty cycle, which demonstrates the maximum current that can be delivered by the ballast 100, 300 at a given frequency. At low light levels, the ballast operating frequency is maintained at the low-end frequency fLOW-END, which is near the resonant frequency of the resonant tank 106. Above a predetermined level, the operating frequency is decreased linearly as the lamp current increases, i.e., as the desired lighting level of the lamp 108 increases towards high-end.
One complication that results from operating the inverter 104 at a frequency that is away from the resonant frequency when utilizing the d(1−d) switching scheme (i.e., at high-end) is the possibility of “mercury pumping”. As the operating frequency moves away from the resonant frequency, and the impedance of the lamp 108 decreases (as the lamp current increases), the filtering effect of the resonant tank 106 is reduced. When the inverter 104 is operating at any duty cycle other than 50%, the voltage at the output of the inverter is asymmetric and contains second harmonic content. For duty cycles near 50%, the second harmonic is not significant. However, as the duty cycle moves away from 50%, the second harmonic content increases.
When operating at the high-end frequency fHIGH-END, a significant amount of this second harmonic content from the inverter 104 is passed through the resonant tank 106 to the lamp 108. As a result, the lamp current is not symmetric. Blocking capacitors, e.g., capacitor 118 in FIGS. 1 and 2, at the output of the ballast 100, 300 prevent the ballast from delivering significant DC current to the lamp 108. However, the asymmetric current in the lamp 108 coupled with the non-linear lamp load results in a DC voltage on the lamp 108. The DC voltage on the lamp 108 will cause mercury ions to migrate from one end of the lamp to the other. If the DC voltage is high enough, the lamp 108 will become starved for mercury at one end. As a result, the starved end of the lamp 108 will produce less light and may also turn pink.
In order to avoid significant mercury pumping, the analog control circuit 210 and the digital control circuit 310 of the prior art ballasts 100, 300 utilized frequency shift profiles that were selected to insure that the duty cycle was as close to 50% as possible when operating at the high-end frequency. However, the tolerances of the components of the resonant tank 106, and the variations in the operating characteristics of common fluorescent lamps, require that the frequency be selected such that even worst-case combinations are capable of reaching the needed high-end current IHIGH-END. The constraints of being able to reach high-end in the worst case while having the highest duty cycle possible result in the need for tight tolerances on components and the need to tailor tank component values to a narrow load range.
Thus, there exists a need for an electronic ballast that avoids mercury pumping and operates at high-end with a duty cycle close to 50% and has a broad range of load types, but does not require a resonant tank that has components with small tolerances.